On a system LSI, a DRAM as a large capacity memory storing data is embedded with a logic circuit. A random access operation as fast as a SRAM is demanded from such an embedded DRAM. Further, since a memory cell consists of one transistor and one capacitor (one transistor plus one capacitor structure) as in the case of a generic DRAM, a bit failure may occur (the manufacturing variation of the contact resistance is a major cause). Therefore, a test as fast as that for the SRAM and a redundancy structure with as many rows and columns as that of the generic DRAM in order to relieve bit failures are needed for the embedded DRAM and so is a technique that tests and applies the both efficiently. In such a technique, testing a memory circuit embedded in a device with a built-in self-test circuit (BIST) without using a tester device (that performs DC/AC test on devices) and replacement by a redundant memory cell is performed by cutting the electric fuse according to the result of the self test.
As an example of a memory having such a redundancy structure, an integrated circuit semiconductor device comprising a built-in self-repair circuit (BISR) for an embedded memory and a method for repairing the memory are disclosed in Patent Document 1. This integrated circuit semiconductor device comprises an embedded memory including multiple row and column redundancies, a built-in self-test circuit (BIST) for detecting faulty memory cells of the memory, and a built-in self-repair circuit for storing information relating to the detected faulty memory cells by dividing information into row information and column information, determining repair methods of repairing the faulty memory cells base on the row information and column information, and generating repaired addresses in the embedded memory. Further, the priority axis is selected according to the number of faulty cells in a two dimensional redundancy parameter. In other words, whether the faulty cells are replaced with redundant memory cells by column or row is determined according to whether multiple faulty cells exist in particular memory cell column or memory cell row.
Further, an on chip self-repair system comprising a row repair circuit for repairing row memory lines having at least one defect and an I/O repair circuit, connected to the row repair circuit, for repairing I/O memory blocks having at least one defect is disclosed in Patent Document 2. And an arbitrator, connected between the row repair circuit and the I/O repair circuit, for implementing a priority scheme is further provided.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-216797A (FIG. 1)
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-A09-311824 (FIG. 1)
The disclosure of the above Patent Documents 1 and 2 are herein incorporated by reference thereto.